In some memory systems, control information such as memory commands and address information are typically generated by a memory controller, and packaged in the form of request packets (e.g., control information multiplexed with address information over a common interconnect resource). An integrated circuit memory device, such as a dynamic random access memory (“DRAM”) device, may receive and translate the information into control signals for a memory core of the memory device.
As memory device bandwidth is increased, scaling or increasing the integrated circuit memory device internal clock frequency to meet an increased bandwidth requirement for processing request packets may unduly increase complexity and power and reduce timing margins of the integrated circuit memory device.